tech-blog

Monday, November 22, 2010

tech blogs forums

SVUG - SystemVerilog User Group
ovmworld - everything related to OVM
OVM world forum
EDA
accelera
http://testbench.in/
testbench blog
verification academy
verification on web
verification horizons
coverification 
Posted by blograma at 3:40 AM No comments:
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Articles on web for systemverilog

Project veripage - good source
project veripage
systemverilog on project veripage
systemverilog queues
systemverilog dynamic arrays
systemverilog interfaces
systemverilog clocking blocks
systemverilog assertions (SVA, ABV)
systemverilog program blocks
systemverilog Parameterized Macro Definition
systemverilog classes
systemverilog cover property
systemverilog structure data type
IPC (Inter Process Communication) in systemverilog
systemverilog interfaces Interface based design
Posted by blograma at 3:29 AM No comments:
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